Electrostatic discharge (ESD) is the main factor that causes electronic components or systems to get damaged by electrical overstress (EOS). Such damage can affect the circuit functions of integrated circuits (ICs) and lead to abnormal operation of the ICs. In order to prevent ICs from adverse ESD effects, an ESD protection arrangement is disposed for the input/output (I/O) pads of ICs to prevent ESD from damaging the ICs. However, for high-voltage I/O pads, it is required in circuit design no PMOS components to connect to the power supply for the pads to sustain voltages higher than the supply voltage, and thereby it is difficult to improve the ESD protection capability of high-voltage I/O pads.
Therefore, an ESD protection arrangement different from the conventional high-voltage I/O pads is desired.